Предлагаю обсудить TSMC наладит серийный выпуск чипов по технологии N4P во второй половине 2022-го
Сколько транзисторов помещается на 1мм²?
Останні статті і огляди
Новини
TSMC наладит серийный выпуск чипов по технологии N4P во второй половине 2022-го
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minesweeper
Member
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Yalg
Member
По паспорту ~173 млн на 5нм.
Two 6T SRAM bitcells were disclosed by TSMC. The high-performance cell is 0.025 µm² while the high-density cell is 0.021 µm². Assuming a ballpark assist circuit overhead of around 30%, the high-density cells yields an estimate of ~32 Mib/mm² of cache. This an increase of 30% from N7 which is around 24.7 Mib/mm².
Two 6T SRAM bitcells were disclosed by TSMC. The high-performance cell is 0.025 µm² while the high-density cell is 0.021 µm². Assuming a ballpark assist circuit overhead of around 30%, the high-density cells yields an estimate of ~32 Mib/mm² of cache. This an increase of 30% from N7 which is around 24.7 Mib/mm².